OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

• Installation
  • Installation steps
    • Step 1. Installation of required packages
      • Instructions for Ubuntu
      • Installation of required packages under macOS
      • Requirements in Containerless/Local Installations
    • Step 2. Making Docker available without root
    • Step 3. Checking the docker installation
      • Troubleshooting of Step 3.
    • Step 4. Checking the requirements
  • Step 5. Downloading and validating OpenLane installation
  • Updating OpenLane
• Quick start
  • Overview
  • Entering the OpenLane environment
  • Creating new designs
  • Running the flow
  • Advanced: Using custom PDK locations and Docker images
  • Advanced: Installing other Standard Cell Libraries
• Configuration Variables
  • Required variables
  • Optional variables
    • Synthesis
    • Floorplanning
      • Deprecated I/O Layer variables
    • Placement
    • CTS
    • Routing
      • Deprecated Layer Adjustment Variables
      • Deprecated Min/Max Layer Variables
      • Removed
    • RC Extraction
    • Magic
    • LVS
    • Misc
    • Flow control
    • Checkers
• Hardening Macros
  • Base Requirements:
  • Synthesis
  • Static Timing Analysis
  • Floorplan
  • IO Placement
  • Placement
    • Global Placement:
    • Optimizations:
      • Resizer optimizations:
    • Detailed Placement:
  • Clock Tree Synthesis
  • Power Grid (pdn)
  • Diode Insertion
  • Routing
  • GDS Streaming
  • Final Reports and Checks
• Contributing
  • Branching
  • Testing and Code Standards
  • Submissions
    • The Approval Process
  • Licensing and Copyright
• Documentation Contributors guide
  • Installation of sphinx for documentation
  • Making screenshots
  • How to contribute
  • Keep trademarks and terms consistent
  • Header’s structure
  • Troubleshooting
    • Your code-block s do not look like they are supposed to
    • Pip module related errors
    • Sphinx build complains about title underline being too short
• Power Grid (pdn)
  • Chip Level:
  • Core Level:
  • Macro Level
• Interactive Mode
• ./flow.tcl Usage
  • Configuration files
    • Replicate/Create Design Configs for a (PDK,STD_CELL_LIBRARY) Pair:
    • Update Design Configs for a (PDK,STD_CELL_LIBRARY) Pair after an Exploration:
• The ECO Flow (Alpha)
  • Flow to Insert Buffer
  • Insert Buffer Command
  • Testcase Results
  • How to enable the ECO flow
• Using OpenLane without Docker
  • Base Requirements
  • Tool Library
  • More about how this works
• Manual PDK Installation
  • Prerequisites
  • Setting up the PDK: skywater-pdk
• OpenLane Interactive Mode Commands
  • General Commands
  • Checker Commands
  • Synthesis/Verilog Commands
  • Floorplan Commands
  • Placement Commands
  • CTS Commands
  • Fill Insertion/Diode Insertion Commands
  • PDN Generation Commands
  • Routing Commands
  • Magic Commands
  • Klayout Commands
  • LVS Commands
  • CVC Commands
  • Utility Commands
• Porting a PDK
  • Folder structure
  • Configuration files
  • PDK Variables
  • Standard cell library-specific variables
  • Tracks Info File
  • PDN Configuration File
  • No Synthesis Cells File
  • DRC Exclude Cells File
• or_issue.py
  • Warning about proprietary files
  • Usage
  • Running or_issue.py manually
• Contributors
  • OpenLane Project Founders
  • OpenLane Core Team
  • All Contributors
  • Special Thanks
• For developers: CI/CD
  • Required Secrets
    • Common
    • CI
    • Tool Updater
• For developers: Building the Docker Image
  • Structure
  • Building the OpenLane Image
  • Updating a Tool Binary
  • Running the newly created Docker image
  • Running as root
• Issue regression tests
  • Issue regression tests flow