OpenLane Architecture

OpenLane Design Stages

OpenLane flow consists of several stages. By default all flow steps are run in sequence. Each stage may consist of multiple sub-stages. OpenLane can also be run interactively as shown here.

1. Synthesis

   1. yosys/abc - Perform RTL synthesis and technology mapping.

   2. OpenSTA - Performs static timing analysis on the resulting netlist to generate timing reports

2. Floorplaning

   1. init_fp - Defines the core area for the macro as well as the rows (used for placement) and the tracks (used for routing)

   2. ioplacer - Places the macro input and output ports

   3. pdngen - Generates the power distribution network

   4. tapcell - Inserts welltap and decap cells in the floorplan

3. Placement

   1. RePLace - Performs global placement

   2. Resizer - Performs optional optimizations on the design

   3. OpenDP - Perfroms detailed placement to legalize the globally placed components

4. CTS

   1. TritonCTS - Synthesizes the clock distribution network (the clock tree)

5. Routing

   1. FastRoute - Performs global routing to generate a guide file for the detailed router

   2. TritonRoute - Performs detailed routing

   3. OpenRCX - Performs SPEF extraction

6. Tapeout

   1. Magic - Streams out the final GDSII layout file from the routed def

   2. KLayout - Streams out the final GDSII layout file from the routed def as a back-up

7. Signoff

   1. Magic - Performs DRC Checks & Antenna Checks

   2. KLayout - Performs DRC Checks

   3. Netgen - Performs LVS Checks

   4. CVC - Performs Circuit Validity Checks

OpenLane integrated several key open source tools over the execution stages:

• RTL Synthesis, Technology Mapping, and Formal Verification : yosys + abc

• Static Timing Analysis: OpenSTA

• Floor Planning: init_fp, ioPlacer, pdn and tapcell

• Placement: RePLace (Global), Resizer and OpenPhySyn (formerly), and OpenDP (Detailed)

• Clock Tree Synthesis: TritonCTS

• Fill Insertion: OpenDP/filler_placement

• Routing: FastRoute or CU-GR (formerly) and TritonRoute (Detailed) or DR-CU

• SPEF Extraction: OpenRCX or SPEF-Extractor (formerly)

• GDSII Streaming out: Magic and KLayout

• DRC Checks: Magic and KLayout

• LVS check: Netgen

• Antenna Checks: Magic

• Circuit Validity Checker: CVC

Everything in Floorplanning through Routing is done using OpenROAD and its various sub-utilities.

OpenLane Output

All output run data is placed by default under ./designs/design_name/runs. Each flow cycle will output a timestamp-marked folder containing the following file structure:

<design_name>
├── config.json/config.tcl
├── runs
│   ├── <tag>
│   │   ├── config.tcl
│   │   ├── {logs, reports, tmp}
│   │   │   ├── cts
│   │   │   ├── signoff
│   │   │   ├── floorplan
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis
│   │   ├── results
│   │   │   ├── final
│   │   │   ├── cts
│   │   │   ├── signoff
│   │   │   ├── floorplan
│   │   │   ├── placement
│   │   │   ├── routing
│   │   │   └── synthesis

To delete all generated runs under all designs: make clean_runs