Reference Manual

• Command-Line Arguments
• Design Configuration Files
  • Initializing a design for use with OpenLane
  • JSON
    • Processing
      • Conditional Execution
      • Variable Reference
      • Expression Engine
  • Tcl
    • Replicate/Create Design Configs for a (PDK,STD_CELL_LIBRARY) Pair:
    • Update Design Configs for a (PDK,STD_CELL_LIBRARY) Pair after an Exploration:
• Configuration Variables
  • Load Order
  • Required variables
  • Optional variables
    • General
      • Macros/Chip Integration
    • Synthesis
    • STA
    • Floorplanning
      • Deprecated I/O Layer variables
    • Resizer (Common)
    • Placement
    • CTS
    • Routing
    • RC Extraction
    • Magic
    • LVS
    • Flow control
    • Checkers
• Tcl Commands
  • General Commands
  • Checker Commands
  • Synthesis/Verilog Commands
  • Floorplan Commands
  • Placement Commands
  • CTS Commands
  • Fill Insertion/Diode Insertion Commands
  • PDN Generation Commands
  • Routing Commands
  • Magic Commands
  • KLayout Commands
  • LVS Commands
  • ERC Commands
  • Utility Commands
• The ECO Flow (Alpha)
  • Flow to Insert Buffer
  • Insert Buffer Command
  • Testcase Results
  • How to enable the ECO flow
• Interactive Mode
• Report Data Definitions
  • Default Printed Information Variables
  • Default Printed Configuration Variables
  • Optional variables