Using OpenLane

• Hardening Macros
  • Base Requirements:
  • Synthesis
  • Static Timing Analysis
  • Floorplan
  • IO Placement
  • Placement
    • Global Placement:
    • Optimizations:
      • Resizer optimizations:
    • Detailed Placement:
  • Clock Tree Synthesis
  • Power Grid/Power Distribution Network
  • Diode Insertion
  • Routing
  • GDS Streaming
  • Final Reports and Checks
• Chip Level Integration
  • The current Methodology
  • Hardening Macros
  • Hardening The Core
  • Hardening The Full Chip
  • Power_routing
    • Macros:
    • Core:
  • General Notes:
• Power Grid/Power Distribution Network
  • Chip Level:
  • Core Level:
  • Macro Level