OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

• Getting Started
  • Installation
    • Installation steps
      • Step 1. Installation of Required Packages
        • Installing Dependencies under Ubuntu
        • Installation of required packages under macOS
      • Step 2. Making Docker available without root
      • Step 3. Checking the Docker Installation
        • Troubleshooting Step 3.
      • Step 4. Checking Installation Requirements
      • Step 5. Download OpenLane
      • Step 6. Download the Docker Image and Install sky130 PDK
      • Step 7. Validating your OpenLane Installation
      • Step 8. Optional: Viewing Test Design Outputs
    • Updating OpenLane
  • Quick start
    • Overview
    • Starting the OpenLane Environment
    • Running the flow
    • Creating new designs
    • Advanced: Using custom PDK locations and OpenLane Docker images
• Using OpenLane
  • Hardening Macros
    • Base Requirements:
    • Synthesis
    • Static Timing Analysis
    • Floorplan
    • IO Placement
    • Placement
      • Global Placement:
      • Optimizations:
        • Resizer optimizations:
      • Detailed Placement:
    • Clock Tree Synthesis
    • Power Grid/Power Distribution Network
    • Diode Insertion
    • Routing
    • GDS Streaming
    • Final Reports and Checks
  • Chip Level Integration
    • The current Methodology
    • Hardening Macros
    • Hardening The Core
    • Hardening The Full Chip
    • Power_routing
      • Macros:
      • Core:
    • General Notes:
  • Power Grid/Power Distribution Network
    • Chip Level:
    • Core Level:
    • Macro Level
• Contributing to OpenLane
  • How to Contribute
    • Branching
    • Testing and Code Standards
    • Choice of Language
      • Tcl
      • Python
    • Yosys, OpenROAD and Magic Scripts
    • Submissions
      • The Approval Process
    • Licensing and Copyright
  • Documentation Contributors guide
    • Introduction
    • Building documentation locally
    • Documentation organization
    • Writing Style and Consistency
      • Terms Consistency
      • Taking screenshots
      • RST Headers
    • Troubleshooting
      • Your code-block s do not look like they are supposed to
      • pip module related errors
      • Sphinx build complains about title underline being too short
  • Porting a PDK
    • Folder structure
    • Configuration files
    • PDK Variables
    • SCL-specific variables
    • Tracks Info File
    • PDN Configuration File
    • No Synthesis Cells File
    • DRC Exclude Cells File
  • or_issue.py
    • Warning about proprietary files
  • Usage
    • Failures
    • Odd Behavior
    • Manually
  • For developers: Building the Docker Image
    • Structure
    • Building the OpenLane Image
    • Updating a Tool Binary
    • Running the newly created Docker image
    • Running as root
  • Issue regression tests
    • Issue regression tests flow
• Reference documentation
  • Variables information
    • Load Order
    • Required variables
    • Optional variables
      • General
      • Synthesis
      • Floorplanning
        • Deprecated I/O Layer variables
      • Placement
      • CTS
      • Routing
      • RC Extraction
      • Magic
      • LVS
      • Flow control
      • Checkers
  • The OpenLane Designs Folder
  • The ECO Flow (Alpha)
    • Flow to Insert Buffer
    • Insert Buffer Command
    • Testcase Results
    • How to enable the ECO flow
  • OpenLane Interactive Mode Commands
    • General Commands
    • Checker Commands
    • Synthesis/Verilog Commands
    • Floorplan Commands
    • Placement Commands
    • CTS Commands
    • Fill Insertion/Diode Insertion Commands
    • PDN Generation Commands
    • Routing Commands
    • Magic Commands
    • Klayout Commands
    • LVS Commands
    • CVC Commands
    • Utility Commands
  • Interactive Mode
• Authors
  • Core Team
  • Core Team Alumni
  • All Contributors
  • Special Thanks